High speed data processing machines typically include an instruction unit that organizes a flow of instructions in a pipeline fashion and an execution unit interlocked with the instruction unit pipeline for executing instructions. Results from the execution of instructions are posted in a result register during a step of the instruction unit pipeline. Before the pipeline can continue wtih the following instructions, the results posted in the result register must be stored to free the result register.
The results are typically loaded from the result register into a storage facility that includes a high speed cache. The high speed cache allows the results to be quickly loaded from the result register into the cache, freeing the instruction unit pipeline to continue the following instructions.
The storage facility also services other sources of data and runs according to a separate pipeline or queue. In prior designs, the flow of the storage unit pipeline for storing results from the result register is required to be a very high priority flow to avoid causing excessive delay in the instruction unit pipeline. Such high priority flows "bump" requests from the storage unit pipeline from other sources. Consequently, a cache contention problem arises.
Prior art systems couple the result register containing data directly to the cache, so the results have to be held in the result register until the operation of transferring the data to the cache is successful. If the line to which the results are to be stored is not present in the cache, the instruction unit pipeline will wait until the storage facility brings the line in from main storage. In this situation, the instruction unit pipeline comes to a halt causing a degradation of performance.
The CACHE STORAGE QUEUE invention referred to above provides an apparatus for transferring data from the result register into a high speed cache that leads to a significant performance enhancement over prior designs and reduces cache contention. The CACHE STORAGE QUEUE provides a plurality of ports that receive data from the result register directly and are able to hold the data in a queue for supply to the cache as the cache resources become available for a store. By transferring the data from the result register into the storage queue ports, the instruction unit is free to proceed with the following instructions before the transfer of the data to the cache is complete.
Other sources of requests for access to cache resources include fetches of data by the instruction unit from the cache, transfers of data between the main storage system and the cache, and processes for other supporting systems utilizing the resources of the storage unit pipeline. The storage unit includes priority logic to select among competing requests for storage unit resources. The request having the highest priority for supply to the storage unit during a given cycle of a pipeline is selected. Thus by priority logic, the utilization of a storage unit resource is controlled.
As mentioned above, it is desirable that the instruction unit pipeline be able to proceed without suffering delays because of inability to obtain priority in the storage unit pipeline. Thus the priority logic is designed to maximize throughput of the instruction unit pipeline.